| 摘要 |
<p>PROBLEM TO BE SOLVED: To enable to insert idle frames and conduct packet read processing at a faster speed by suppressing the increase of circuit scale. SOLUTION: A packet data arrangement control circuit 1 is provided with FIFO memories 19-11-19-1M-19-N1-19-NM that store data bytes in M-byte width resulting from parallel processing applied to variable length packets in the unit of M sets without a gap by each logical channel in a state that pad bytes between user packet frames of the variable length packet are eliminated. An updated storage byte number Q is updated and calculated according to expression of Q=Q+W-R newly based on a written data byte number W stored in all the FIFO memories of the logical channel, a read data byte number R read therefrom, and a stored byte number Q.</p> |
