发明名称 CLOCK ADJUSTER USED IN DATA REPRODUCING DEVICE, OFFSET DETECTOR AND DATA REPRODUCING DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a clock adjuster stably adjusting a phase. SOLUTION: The clock adjuster is provided with a phase error detection means detecting the phase error amount of a clock on the basis of the state of a sampling value at the rising edge of reproducing signals with a reference level as a reference, a reference level adjusting means adjusting the reference level used in the phase error amount detection means on the basis of an offset amount and a phase adjusting means adjusting the phase of the clock on the basis of the phase error amount. An offset detection means is provided with a monitoring sampling value generation means generating a monitoring edge sampling value on the basis of the sampling value at the falling edge of the reproducing signals and an offset computing means computing the change amount of the successively generated monitoring edge sampling values with the monitoring edge sampling value obtained at a prescribed timing as the reference as the offset amount.
申请公布号 JP2002358734(A) 申请公布日期 2002.12.13
申请号 JP20010165589 申请日期 2001.05.31
申请人 FUJITSU LTD;FUJITSU PERIPHERALS LTD 发明人 HAMADA KENICHI;FURUTA SATOSHI;YANAGI SHIGETOMO
分类号 G11B20/14;G11B7/005;G11B20/10;(IPC1-7):G11B20/14 主分类号 G11B20/14
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