| 摘要 |
PROBLEM TO BE SOLVED: To improve operation speed of a semiconductor device by sufficiently reducing parasitic capacitance added to the semiconductor device. SOLUTION: A dummy gate electrode is formed in a dummy gate electrode forming process (step S2), a side wall is formed on a side wall of the dummy gate electrode in a side wall forming process (step S4), an interlayer insulating film is deposited in a deposition process of a first interlayer insulating film (step S6), a surface of the interlayer insulating film is flattened in a flattening process of the first interlayer insulating film (step S7), the dummy gate electrode is eliminated in a dummy gate electrode eliminating process (step S8), a gate electrode is formed on a formation marked part of the dummy gate electrode which has been eliminated in a gate electrode forming process (step S9), and the side wall is eliminated and a gap is formed between a side wall of the gate electrode and the interlayer insulating film in a side wall eliminating process (step S10).
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