发明名称 INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce the delay of output signal in LSI actual operation in an integrated circuit for performing the operation test of an internal circuit such as CPU core or the like within LSI by use of an external terminal used in the LSI actual operation. SOLUTION: A multiplexer 28 for switching the signal output route of a JTAG resistor to the signal output route of a CPU core 3 and a multiplexer 27 for switching the signal output route of a controller to the signal output route of the multiplexer 28 are provided on a boundary scan circuit 16, whereby the delay of output signal of the controller 11 in LSI actual operation can be reduced to the share of one multiplexer.
申请公布号 JP2002357639(A) 申请公布日期 2002.12.13
申请号 JP20010167411 申请日期 2001.06.01
申请人 TOSHIBA CORP 发明人 KATO YOSHIYUKI
分类号 G01R31/28;H01L21/822;H01L27/04;(IPC1-7):G01R31/28 主分类号 G01R31/28
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