发明名称 Variable cycle interrupt disabling
摘要 A processor processes a variable cycle interrupt disable instruction DISI X is provided. The instruction disables interrupt processing for a variable number of processor cycles corresponding to the value specified by the instruction operand X. The DISI X instruction may be strategically used by programmers to prevent interrupts from being taken during certain intervals within a program.
申请公布号 US2002188784(A1) 申请公布日期 2002.12.12
申请号 US20010870447 申请日期 2001.06.01
申请人 BOLES BRIAN;TRIECE JOSEPH W.;CONNER JOSHUA M. 发明人 BOLES BRIAN;TRIECE JOSEPH W.;CONNER JOSHUA M.
分类号 G06F13/24;(IPC1-7):G06F13/24 主分类号 G06F13/24
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