A processor is provided that has a data memory that may be addressed as a dual memory space in one mode and as a single linear memory space in another mode. The memory may permit dual concurrent operand fetches from the data memory when DSP instructions are processed. The memory may then dynamically permit the same memory to be accessed as a single linear memory address space for non-DSP instructions.
申请公布号
WO02099634(A1)
申请公布日期
2002.12.12
申请号
WO2002US16970
申请日期
2002.05.30
申请人
MICROCHIP TECHNOLOGY INCORPORATED
发明人
CATHERWOOD, MICHAEL;TRIECE, JOSEPH, W.;PYSKA, MICHAEL;CONNER, JOSHUA, M.