| 摘要 |
A digital quadrature signal detecting circuit constituted by a digital signal delay circuit for forming an in-phase (I) signal by delaying a digital signal outputted from an analog/digital conversion part for analog/digital converting a received signal having a non-zero center frequency by a predetermined sampling frequency, and a digital all-pass filter for forming a quadrature (Q) signal by shifting a phase of the digital signal by 90°, wherein the digital all-pass filter is an infinite impulse response digital filter having a definite group delay frequency characteristic, and the digital signal delay circuit has a signal delay amount equal to a group delay amount of the digital all-pass filter.
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