发明名称 |
Voltage controlled oscillation circuit |
摘要 |
Backgate biases of MOS transistors for generating a bias voltage in a bias voltage generation circuit generating the bias voltages are set shallow and backgate biases of MOS transistors of delay circuits of a ring oscillator constituting a clock generation circuit are set shallow. Thereby, a voltage range and a frequency range of a voltage controlled generation circuit to implement a phase synchronizing loop are both extended.
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申请公布号 |
US2002186072(A1) |
申请公布日期 |
2002.12.12 |
申请号 |
US20020120572 |
申请日期 |
2002.04.12 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
MANO RYUJI;NOTANI HIROMI |
分类号 |
H03K3/012;H03K3/03;H03L7/099;(IPC1-7):G05F1/10 |
主分类号 |
H03K3/012 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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