| 摘要 |
<p>A semiconductor storage device capable of efficiently reducing power consumption of a circuit system related to refresh operation. In the refresh operation interval, a control signal circuit (2) controls by an internal chip select signal (CSI) Nch transistors (3C, 4B) connected between the circuit system related to the refresh (internal step-down circuit (3) and a boost circuit (4)) and the ground so as to be in the off state. This cuts off the leak route of the circuit system related to the refresh operation and reduces the leak current. Moreover, when a timing to activate refresh by the timer as a trigger has come, the internal chip select signal (CSI) is made H level and the internal step-down circuit (3) and the boost circuit (4) are grounded</p> |
