DCC CIRCUIT AND METHOD FOR CORRECTING AND MAINTAINING DUTY CYCLE

摘要

PURPOSE: A DCC(Duty Cycle Corrector) circuit and a method for correcting and maintaining a duty cycle are provided to reduce a time for correcting a duty of a clock signal and maintain previous information and signals though the power is not supplied to a circuit. CONSTITUTION: A D/D(Duty Detector) block(42) receives a corrected clock signal, a digital input signal, a reference signal, and the first control signal for intercepting power and outputs a detection result signal using the first comparing result signal. The first comparing result signal is generated by comparing the digital input signal or the corrected clock signal with the reference signal. A sense amplifier(44) sensing and amplifying an output signal of the D/D block(42). An accumulator(46) is used for accumulating output signals of the sense amplifier(44) according to the second control signal and outputs the accumulated data. A duty cycle corrector(48) outputs a corrected signal of the digital input signal to the D/D block(42) according to an output signal of the accumulator(46).