发明名称 VITERBI DECODER
摘要 <p>It is an object to provide a Viterbi decoder whereby the error correction characteristic is improved whilst enlargement in system scale is suppressed. For this purpose, a bit range converter(11) for converting the bit range of the branch metric values calculated by a branch metric calculator(1) to meet the number of calculation bits used in an ACS portion(2) is provided between branch metric calculator(1) and ACS portion(2) while the decoder reads the received data and calculates the branch metrics, optimizes the branch metrics and change the path metric and store it into the path memory until the frame is completed and when one frame has been completed then it outputs the decoded result by backtracing. &lt;IMAGE&gt;</p>
申请公布号 EP1265367(A1) 申请公布日期 2002.12.11
申请号 EP20000908047 申请日期 2000.03.14
申请人 SHARP KABUSHIKI KAISHA 发明人 KISHINO, MASAHIKO
分类号 H03M13/41;(IPC1-7):H03M13/41 主分类号 H03M13/41
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