| 摘要 |
PURPOSE: A non-volatile semiconductor memory device having a selective speed operation mode is provided to operate selectively more page sizes and a two or more block sizes according to a user's option by forming a NAND type flash memory device. CONSTITUTION: A plurality of cell arrays(200,210) are used for forming memory cell arrays. A plurality of row decoders(230,231,240,241) receive row pre-decoding signals and select word lines of the cell arrays(200,210). The first and the second page buffers(250,251) are connected with bit lines of the cell arrays(200,210) in order to receive or output data from or to the selected memory cell transistors. The first and the second Y gates(260) select the first and the second page buffers(250,251) in response to column pre-decoding signals. An I/O buffer and latch(270) are connected with the first and the second Y gates(260) in order to buffer and latches the input/output data. An I/O portion(280) is connected with the I/O buffer and latch(270). A row pre-decoder(100) applies the row pre-decoding signals to the row decoders(230,231,240,241). A control logic and high voltage generator(110) controls the row decoders(230,231,240,241) and applies a high voltage. A page buffer control logic(120) controls the first and the second page buffers(250,251). A column pre-decoder(130) applies the column pre-decoding signals to the first and the second Y gates(260,261). A command register(140) is connected with the I/O buffer and latch(270).
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