发明名称 |
Processor having replay architecture with fast and slow replay paths |
摘要 |
According to one aspect of the invention, a microprocessor is provided that includes an execution core, a first replay mechanism and a second replay mechanism. The execution core performs data speculation in executing a first instruction. The first replay mechanism is used to replay the first instruction via a first replay path if an error of a first type is detected which indicates that the data speculation is erroneous. The second replay mechanism is used to replay the first instruction via a second replay path if an error of a second type is detected which indicates that the data speculation is erroneous.
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申请公布号 |
GB2376328(A) |
申请公布日期 |
2002.12.11 |
申请号 |
GB20020021325 |
申请日期 |
2000.12.29 |
申请人 |
* INTEL CORPORATION |
发明人 |
MICHAEL D * UPTON;DAVID J * SAGER;DARRELL D * BOGGS;GLENN J * HINTON |
分类号 |
G06F9/38;(IPC1-7):G06F9/38;G06F11/07 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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