发明名称 |
CMOS state saving latch |
摘要 |
A state saving circuit and method for using the same. The circuit comprises a first latch powered by an uninterrupted power supply, wherein the first latch includes a first pair of cross coupled inverters for storing data, and includes an input cut-off control for isolating the data in the first pair of cross coupled inverters; a second latch coupled to an output of the first latch and powered by an interruptible power supply, wherein the second latch includes a second pair of cross coupled inverters and a clock input for latching the data from the first latch to the second latch; and wherein an interruption of power to the second latch results in a state being saved in the first latch.
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申请公布号 |
US6493257(B1) |
申请公布日期 |
2002.12.10 |
申请号 |
US20020108687 |
申请日期 |
2002.03.27 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
COUGHLIN, JR. TERRY C.;GREGOR ROGER P.;OAKLAND STEVEN F.;STOUT DOUGLAS W. |
分类号 |
G11C14/00;(IPC1-7):G11C11/412 |
主分类号 |
G11C14/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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