发明名称 |
Method and apparatus for scheduling and using memory calibrations to reduce memory errors in high speed memory devices |
摘要 |
A computer system with high-speed memory devices includes error checking logic that monitors the number and/or frequency of memory errors. The number and/or frequency of soft memory errors is provided to control logic in a memory controller, which intelligently modifies the frequency of memory calibration cycles based on the detected memory errors. Thus, in response to an unacceptable number of memory errors, the memory controller may increase the frequency of calibration cycles. The memory controller may include error checking logic that monitors memory errors on multiple memory channels, if multiple memory channel are provided, to enable the memory controller to modify calibration frequency on a channel-by-channel basis.
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申请公布号 |
US6493836(B2) |
申请公布日期 |
2002.12.10 |
申请号 |
US20000726738 |
申请日期 |
2000.11.30 |
申请人 |
COMPAQ INFORMATION TECHNOLOGIES GROUP, L.P. |
发明人 |
OLARIG SOMPONG P.;JENNE JOHN E. |
分类号 |
G06F11/00;G06F11/10;G06F11/30;G11C11/4193;G11C29/44;(IPC1-7):G06F11/30;G11C11/419 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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