发明名称 Method for manufacturing semiconductor device capable of suppressing narrow channel width effect
摘要 In a method for manufacturing a semiconductor device, a shallow trench isolation layer made of silicon oxide is formed in a semiconductor substrate to partition an area for forming a MOS transistor. Then, first impurities are introduced into the MOS transistor forming area to adjust a threshold voltage of the MOS transistor. Then, second impurities are introduced into end portions of the MOS transistor forming area of the semiconductor substrate.
申请公布号 US6492220(B2) 申请公布日期 2002.12.10
申请号 US20000578556 申请日期 2000.05.25
申请人 NEC CORPORATION 发明人 IKEDA MASAHIRO
分类号 H01L21/76;H01L21/425;H01L21/762;H01L21/8238;H01L27/092;H01L29/78;(IPC1-7):H01L21/76 主分类号 H01L21/76
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