| 摘要 |
An FPGA architecture and method to reduce the size of the bitstream used in configuring or reconfiguring the FPGA. To facilitate features of the compression process, an FPGA is modified to implement an addressable data register in place of a conventional shift register. This allows data frames to be arranged in order of similarity, and a bitstream formed from one full data frame along with an address into which the frame is to be loaded, and subsequent partial data frames including only changed words along with the row address of the changes and the column address into which modified frames are to be loaded, rather than shifting in entire frames of data for subsequent frames.
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