发明名称 Multi-tier point-to-point buffered memory interface
摘要 Methods and apparatus for a memory system using a branching point-to-point memory bus architecture are disclosed. In one embodiment, a primary memory controller maintains a point-to-point bus connection with one memory module and that memory module maintains a separate point-to-point bus connection with a second module. Data passing between the memory controller and the second memory module passes through a buffer circuit on the first memory module. For data received from the memory controller, the buffer circuit also passes that data up a module bus segment to a first bank of memory devices. That bank of memory devices maintains a second module bus segment with a second bank of memory devices. Data passing between the buffer circuit and the second bank of memory devices passes through a pass-through circuit on the first bank of memory devices. In this manner, a point-to-point memory bus architecture can be maintained even when a memory module contains more than one bank of memory devices.
申请公布号 US6493250(B2) 申请公布日期 2002.12.10
申请号 US20000753024 申请日期 2000.12.28
申请人 INTEL CORPORATION 发明人 HALBERT JOHN B.;DODD JAMES M.;LAM CHUNG;BONELLA RANDY M.
分类号 G06F13/42;(IPC1-7):G11C5/06 主分类号 G06F13/42
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