Pre-divider architecture for low power in a digital delay locked loop

摘要

A delay locked loop circuit for conserving power on a semiconductor chip is provided. The circuit includes a delay chain circuit responsive to a clock input signal for generating an output clock signal having a selectively adjustable delay at an output circuit; a feedback loop circuit connects to and controls said delay chain circuit; and a pre-divider circuit connected to said delay chain circuit, wherein said pre-divider circuit is configured to disable the delay chain circuit when the output clock signal is inactive and the memory device is in an idle state (i.e., all banks closed).