| 摘要 |
Hardware Verification Languages (HVLs) permit the convenient modeling of the environment for a device under test (DUT). HVLs permit the DUT to be tested by stimulating certain inputs of the DUT and monitoring the resulting states of the DUT. The present invention relates to an HVL, referred to as Vera, for the verification of any form of digital circuit design. Vera is preferably used for testing a DUT modeled in a high-level hardware description language (HLHDL) such as Verilog HDL. More specifically, the present invention relates to an HVL capability, know as an "expect," for monitoring the values at certain nodes of the DUT at certain times and for determining whether those values are in accordance with the DUT's expected performance. In particular, upon the first occurrence of a transition on one of the DUT's nodes, since beginning a window period of monitoring, the expect will either generate an error if the DUT's output is unexpected, or proceed with modeling the DUT's environment if the output is expected. A delay may be specified, which will delay the expect's initiation of the window monitoring period.
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