HIGH-SPEED SENSE LATCH CIRCUIT

摘要

A sense latch circuit having a short access time. The latch output switches state rapidly due to the incorporation of a minimum number of logic stages between the sense inputs and the output drive stage, thereby introducing a minimum number of delays. Nonsaturable logic circuits are utilized to allow fast switching. At the inputs of the sense latch circuit, the high DC levels of the sense signals are reduced in magnitude for application to an ECL circuit switch with the use of diodes and resistor dividers. This arrangement allows for large temperature variations without saturating any of the logic stages.