| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock control circuit with reduced circuit scale. SOLUTION: The clock control circuit is provided with a ring counter 100 that outputs an N-bit signal and its complementary signal, an unexpected relief and flag generating circuit 150 that relieves an unexpected pattern and generates a flag signal JBTFLG with a value corresponding to a combination of 2N-bit signals, a decode circuit 160, a clock selector that outputs a clock pair from a polyphase clock on the basis of a selection control signal from the decode circuit, an interpolator 130 that outputs a signal with a delay time corresponding to a time resulting from internally dividing a phase difference of the clock pair, a phase comparator 110 that compares an output of the interpolator with a phase of a reference clock, and an interpolator control circuit 120 that varies a shift direction on the basis of the phase comparison result from the phase comparator and the flag signal JBTFLG and outputs an internal division ratio control signal to set an internal division ratio of the interpolator. |
