| 摘要 |
PROBLEM TO BE SOLVED: To stop supply of a clock to operate a shift register except a in time point when data are fetched into the shift register by executing an arithmetic operation and a point in time when an arithmetic result is transmitted. SOLUTION: Establishment of AND conditions of an AND gate 6 is evaded by performing OFF output of a logical gate 7 except when either of a signal (ADD) and a signal (NEXT) is at H (high level). Since an output supply clock (SC) is not supplied, that is, at L (low level) while the AND conditions of the AND gate 6 is not established, the shift register 3 is not actuated and simply holds data. Consequently, power consumption in the shift register 3 is saved in this period. The signal (NEXT) is actuated for the next stage as a signal equivalent to the signal (ADD) from the previous state. |
