发明名称 POWER CHIP SCALE PACKAGE
摘要 <p>PROBLEM TO BE SOLVED: To provide a packaging configuration for a semiconductor device including a lead frame and a die connected thereto. SOLUTION: The die is connected to the lead frame so that the rear face (drain area) is in the same plane as a source lead and a gate lead extending from the lead frame. A reinforcing material is connected to the lead frame, electrically insulated therefrom, and helps to maintain the source and gate pad positions of the lead frame. The semiconductor device is connected to a printed circuit board(PCB), the exposure face of the die is directly worked as drain connection, and the source lead and the gate lead are worked as connection for the source and gate areas of the die.</p>
申请公布号 JP2002353373(A) 申请公布日期 2002.12.06
申请号 JP20020139486 申请日期 2002.05.15
申请人 FAIRCHILD SEMICONDUCTOR CORP 发明人 ESTACIO MARIA CRISTINA B;MADRID RUBEN
分类号 H01L23/12;H01L23/495;(IPC1-7):H01L23/12 主分类号 H01L23/12
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