| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a digital signal compressing circuit and a digital signal expanding circuit with low power consumption. SOLUTION: The digital signal compressing circuit is constituted in such a manner that the circuit is provided with a subtractor 1 for taking a difference between an image signal and a prediction signal, a discrete cosine transformer 2 and quantizer 3 for compressing and quantizing the difference, an inverse quantizer 4 and an inverse discrete cosine transformer 5 for making the output from the quantizer 3 back to the original difference, an adder 6 for adding the difference to a prediction signal to form an accumulated frame signal, an accumulated frame memory 7 for storing the accumulated frame signal, a basic signal memory 19 for storing a basic frame signal, and a selector 20. The selector 20 selects an output from the memory 19 as a prediction signal when transmitting an I frame, and selects an output from the memory 7 as a prediction signal when transmitting frames other than the I frame.</p> |
