| 摘要 |
A single bitline direct sensing architecture employs a 4 transistor sense amplifier circuit located in each memory array, wherein the transistors function to selectively transfer data bits from either a true bitline or a complement bitline of the bitline pair to a data line. The data line is preferably arranged over a plurality of memory arrays. The data line may or may not be shared for the read and write operations. One current source is additionally used to precharge the datalines in a read mode, performing the function of a digital sensing scheme by detecting a resistance ratio between the current source and the transistor driven by the bitline for the corresponding array. A simple inverter may be used for detecting a level of the data line determined by the resistance ratio. The bitline pair is sensed in a single ended fashion, eliminating the need for a cross-coupled pair of CMOS devices, and thus reducing the required layout area. By accessing the bitline pair individually, two sets of control signals for the pre-charge, EQ0, EQ1, are developed to allow for bitline shielding in the array. This technique greatly reduces bitline to bitline coupling noise which is a concern for high speed, low cycle time memory applications. The simplicity of this single bitline architecture allows all data bit in a memory array to be transferred to the corresponding data lines, resulting in an ultimate bandwidth. The read and write data lines may be arranged with a pitch exactly the same as the bitline pitch. This thus makes it possible to transfer all of the data bits to the corresponding read data lines in a first memory array, while receiving all of the data bits from the corresponding write data lines in a second memory array.
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