| 摘要 |
PURPOSE: To obtain a semiconductor device where the increase of gate capacitance is restrained to a minimum, without exerting adverse influence upon operating characteristics, and a manufacturing method of the device. CONSTITUTION: First trenches 7 and second trenches 11 are formed penetrating an N¬- layer 3 and an N layer 4 and reaching an upper layer part of the N¬- layer 3. In this case, a prescribed number of the second trenches 11 are formed between the first trenches 7 and 7. The first trench 7 is adjacent to N¬+ emitter region 6, and a gate electrode 9 is formed in the inside. A polysilicon region 15 is formed in the second trench 11, which is different from the first region 7 in the point that the N¬+ emitter region 6 is not formed in the adjacent region, and the gate electrode 9 is not formed in the inside. The interval between the first trench 7 and the second trench 11, which are adjacent to each other is set so that a withstand voltage will not decrease. An emitter electrode 12 is formed directly over almost the whole surface of a base region 5.
|
