发明名称 |
Clock distribution circuit |
摘要 |
A user circuit unit is configured by a gate array, a PLT circuit is configured in a microprocessor macro unit, a clock frequency output from the PLL circuit in the microprocessor macro unit is directly distributed to auser circuit unit (CLK 3), and the clock frequency distributed to the user circuit unit is distributed to the microprocessor macro unit through a frequency divider configured by the user circuit unit.
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申请公布号 |
US2002180502(A1) |
申请公布日期 |
2002.12.05 |
申请号 |
US20020127297 |
申请日期 |
2002.04.22 |
申请人 |
AOKI YOSHITAKA;IDA NOBUO;HIKIBA RUMI;NAKAJIMA YOSHINOBU |
发明人 |
AOKI YOSHITAKA;IDA NOBUO;HIKIBA RUMI;NAKAJIMA YOSHINOBU |
分类号 |
G06F17/50;G06F1/10;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):H03K5/01 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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