| 摘要 |
The period of time required for a parallel test can be shortened by widening the application range of the parallel test. In the semiconductor memory device having a memory cell portions (5-A, 5-B), there are provided a column control means (1~4) for simultaneously activating a plurality of columns which are subject to the degenerate substitution in the column redundant substitute; and a data read-out means (6-A, 6-B, SDBP-B0, SDBP-B1, and 9) for simultaneously reading out the data from a plurality of memory cells as selected by the above plurality of columns.
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