发明名称 Direct digital synthesizer phase locked loop
摘要 Phase locked loops adapted to filter and store data indicative of the control signal applied to an oscillator permit suppression of tracking in the event of a step change in the phase difference between the reference clock signal and the feedback signal in the phase locked loop. Such phase locked loops further facilitate compensation for drift of the oscillator. Such phase locked loops are suitable for use in timing circuits of communications systems.
申请公布号 US2002180498(A1) 申请公布日期 2002.12.05
申请号 US20020087521 申请日期 2002.03.01
申请人 O'LEARY WILLIAM;ROWAND EDWIN W. 发明人 O'LEARY WILLIAM;ROWAND EDWIN W.
分类号 H03L7/099;H03L7/14;H03L7/18;H03L7/199;H04J3/06;(IPC1-7):H03L7/06;H03L7/00 主分类号 H03L7/099
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