SOI LDMOS TRANSISTOR HAVING A FIELD PLATE AND METHOD OF MAKING THE SAME

摘要

A method and structure for a Silicon-on-Insulator transistor device such as Loi-LDMOS or Soi-LIGBT with a lateral drift region (32) and a conducting top field plate (44, 44a) is presented. The method consists of decreasing the gate to drain capacitance (301, 401) by means of decreasing the portion of the filed plate (44, 44a) that is connected to the gate electrode (36, 36a), and hence the effective overlap of the gate (36, 36a) with the drift region (32) and drain (34). This results in decreased energy dissipation in switching the transistor, and more efficient operation. The rate of decrease of the gate to drain capacitance (301, 401) is even faster at higher drain voltages, inuring in significant energy efficiencies in high voltage applications.