发明名称 |
IC ANALYSIS SUPPORT METHOD,IC ANALYSIS APPARATUS,IC ANALYSIS SUPPORT PROGRAM |
摘要 |
An IC analysis support method in which a wiring path is extracted only from CAD layout data which is design information on an IC as a device to be tested and the extracted wiring path is highlighted when displayed, facilitating to navigate (survey) a defect, and an IC analysis apparatus using the method. The IC analysis support method in which layout data of CAD data is received by a computer and a wiring path is displayed comprises a step for judging whether a viahole exists in the overlapping portion between a first polygon and a second polygon constituting the wiring path and a step for recognizing the first polygon and the second polygon as one wiring path if a viahole is found.
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申请公布号 |
WO02097459(A1) |
申请公布日期 |
2002.12.05 |
申请号 |
WO2002JP05205 |
申请日期 |
2002.05.29 |
申请人 |
ADVANTEST CORPORATION;HIRAYAMA, YUKI;NIIJIMA, HIRONOBU;MURAKAWA, TSUTOMU |
发明人 |
HIRAYAMA, YUKI;NIIJIMA, HIRONOBU;MURAKAWA, TSUTOMU |
分类号 |
G01R31/28;(IPC1-7):G01R31/28;H01L21/66 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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