发明名称 Method for manufacturing contacts for a Chalcogenide memory device
摘要 A method for manufacturing contacts for a Chalcogenide memory device is disclosed. A via is initially formed within a first oxide layer on a substrate. A conductive layer is then deposited on top of the first oxide layer. A second oxide layer is deposited on the conductive layer. Subsequently, the second oxide layer and the conductive layer are then removed such that the remaining portion of conductive layer within the via flushes with a surface of the first oxide layer. A third oxide layer is deposited on the conductive layer, and the first and second oxide layers. A pattern is formed to remove third layer so that the pattern opens orthgonally across and exposes the conductive layer. Next, a nitride layer is deposited on the third oxide layer, the conductive layer, and the first and second oxide layers. The nitride layer conforms with the contour of the third oxide layer. After directionally removing the nitride layer to form a spacer at the exposed edge of the third oxide layer, the third oxide layer is removed to expose the spacer. The conductive layer is then etched to remove a portion of the conductive layer not underneath the spacer. The portion of the conductive layer underneath the spacer resembles a matchstick. The spacer is then removed to expose the matchstick-like conductive layer portion with a small top surface contact area.
申请公布号 US2002182835(A1) 申请公布日期 2002.12.05
申请号 US20010867120 申请日期 2001.05.29
申请人 QUINN ROBERT M. 发明人 QUINN ROBERT M.
分类号 H01L21/768;H01L45/00;(IPC1-7):H01L21/20;H01L21/44;H01L21/00;H01L21/28;H01L21/320 主分类号 H01L21/768
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