发明名称 NON-BLOCKING VIRTUAL SWITCH ARCHITECTURE
摘要 A non-blocking virtual switch architecture (Fig. 5) for a data communication network. The switch includes a plurality of input ports and output ports. Each input port may be connected directly to each output port by a directly connected network or by a mesh network. Thus, data packets may traverse the switch simultaneously with other packets. At each output port (618), buffer space is dedicated for queuing packets received from each of the input ports (Port A in-Port D in). An arbitration scheme is utilized to forward data from the buffers to the network. Accordingly, the use of a crossbar array, and associated bottle necks, are avoided. Rather, the system advantageously provides separate buffer space at each output port for every input port.
申请公布号 WO02056526(A3) 申请公布日期 2002.12.05
申请号 WO2001US50565 申请日期 2001.12.20
申请人 MAPLE OPTICAL SYSTEMS, INC. 发明人 KU, ED;KOTHARY, PIYUSH;CHATTOPADHYA, SANDIP;HAGENE, STEFFEN
分类号 H04L12/24;H04L12/46;H04L12/56 主分类号 H04L12/24
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