| 摘要 |
The desynchronizer (10) of the present invention includes two FIFOs. The first FIFO has two address counters (read and write), an intermediate count register (26), circuitry (for calculating the difference between the write and the intermediate counts and the intermediate and read counts, a logic block for performing pointer leak and other arithmetic functions and digitally controlled oscillator. The second FIFO has read and write counters, a phase-frequency detector (54), and an internal VCO (58) controlled by length measurements of the second FIFO. The desynchronizer (10) receives data bits, pointer movement indications, and stuff indications from a DS-3/E3 demapper and, using the first FIFO, the address counters, etc., removes the low frequency components, including SONET/SDH systemic gapping in order to provide the second FIFO with a DS-3/E3 signal having a high frequency phase modulation. The second FIFO removes the remaining high frequency gapping jitter.
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