| 摘要 |
The invention provides a semiconductor memory device incorporating memory cells the same as for DRAM and which operates under SRAM specification, where the chip size is small and power consumption and cost are low, and for which access delay or memory cell data destruction due to skew incorporated in an address does not arise. An ATD circuit (3) generates a one shot pulse for an address transition detection signal (ATD) from transition of an externally supplied address (Address). At this time, by generating the one shot pulse for each bit of the address and then combining these, then even in the case where the address contains a skew, the one shot pulse is only generated once. At first, refresh is performed during the generation period of the one shot pulse, using a refresh address (R_ADD) generated by a refresh control circuit (4). Then, on receipt of a fall in the one shot pulse, a latch control signal (LC) is generated, the address is latched by the latch (2) and the memory cell array (6) accessed.
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