In one embodiment, a programmable processor includes a execution pipeline and an exception pipeline. The execution pipeline may be a multi-stage execution pipeline that processes instructions. The exception pipeline may be a multi-stage exception pipeline that propagates exceptions resulting from the execution of the instructions. The first and exception pipelines may have the same number of stages and may operate on the same clock cycles. When an instruction passes from a stage of the execution pipeline to a later stage of the execution pipeline, an exception may similarly pass from a corresponding stage of the exception pipeline to a corresponding later stage of the exception pipeline.
申请公布号
WO0248873(A3)
申请公布日期
2002.12.05
申请号
WO2001US47626
申请日期
2001.12.10
申请人
INTEL CORPORATION;ANALOG DEVICES, INC.
发明人
ROTH, CHARLES, P.;SINGH, RAVI, P.;OVERKAMP, GREGORY, A.