| 摘要 |
The invention, in one embodiment, is a processor pipeline. The pipeline includes a front end, a back end, and a queue between the front end and the back end. The queue is capable of storing an intermediate state of the processor from which the back end may be replayed. The invention, in another embodiment, is a micro-op queue storing an intermediate state of a pipeline in a processor from which a back end replay can be instituted. |
