发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, an address for salvaging a defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit. As a result, a special process is not needed in forming the nonvolatile memory element. In other words, the nonvolatile memory element can be formed in a process of forming a CMOS device and an apparatus of a laser beam for programming is not needed since the programming is carried out in testing. Thus, the time necessary for programming can be shortened, and, therefore, testing costs can be reduced.
申请公布号 EP1262996(A1) 申请公布日期 2002.12.04
申请号 EP20010904349 申请日期 2001.02.08
申请人 HITACHI, LTD. 发明人 ISHIBASHI, KOICHIRO;SYUKURI, SHOJI;YANAGISAWA, KAZUMASA;NISHIMOTO, JUNICHI;YAMAOKA, MASANAO;AOKI, MASAKAZU
分类号 G11C29/00;H01L21/8247;G11C16/04;G11C29/04;G11C29/12;G11C29/42;H01L21/66;H01L23/532;H01L23/544;H01L27/02;H01L27/105;H01L27/108;H01L29/788;H01L29/792 主分类号 G11C29/00
代理机构 代理人
主权项
地址