Logic verification method and apparatus for logic verification

摘要

After a logic verification is made in a low-hierarchical block, a logic verification is made in a high-hierarchical block circuit in a state that the low-hierarchical block is not the subject of comparison. Even if the number of input ports in the low-hierarchical block increases due to a change of the circuit, logical equivalence of the high-hierarchical circuit is verified by using equivalence information of the input ports.