| 摘要 |
Match lines of a CAM array are grouped into sets and provided to corresponding match and priority encoding logic (MPL) circuits. Each MPL circuit includes an input connected to an output of a previous MPL circuit. The last MPL circuit has an output connected to a control circuit. In response to the set of match signals, each MPL circuit generates a match flag and the index of the highest priority match for the set. In response to the match flags, the control circuit provides a plurality of select signals to corresponding MPL circuits each of which, in response to its select signal, provides either the set index generated therein or a set index received from the previous MPL circuit to the next MPL circuit. The select signals are asserted so that the index of the highest priority match line set ripples through the MPL circuits to the control circuit.
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