| 摘要 |
A selective memory refresh circuit for refreshing a memory cell array. The memory cell array has a plurality of word lines connected to a plurality of word line selection circuits for determining if a particular word line needs to be refresh during a refresh cycle. Each word line refresh selection circuit further has a word line address latching device for receiving a word line pre-decode signal, a release signal, a triggering signal and outputting a word line latching signal and a word line refresh compare circuit for receiving the word line pre-decode signal and the word line latching signal and transmitting the result of comparison to a word line driver. When the word line latching signal is at a high level, memory cells attached to the word line are refreshed. On the contrary, when the word line latching signal is at a low level, memory refresh for that word line is skipped.
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