| 摘要 |
A semiconductor memory circuit including a plurality of bit lines, memory cells connected to each of said plurality of bit lines, sense amplifiers, each corresponding to one of said plurality of bit lines and each configured to amplify a voltage of the corresponding bit line, dummy bit lines, a plurality of dummy cells connected to said dummy bit lines, a dummy sense amplifier configured to output signals with voltages obtained by amplifying the voltages of said dummy bit lines, and to set an activation timing of said sense amplifier based on the output, and a dummy cell selecting circuit configured to simultaneously select at least two of the dummy cells, when the sense amplifier is activated.
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