发明名称
摘要 A clamping divider has a bit shifter, a multiple accumulator (MAC), and an output circuit. When executing a division with the use of a clamp value of 2m, the bit shifter shifts one of the divisor and dividend of the division, and the MAC subtracts the shifted one from the other to determine, before calculating a quotient of the division, whether or not a result of the division must be clamped.
申请公布号 JP3352887(B2) 申请公布日期 2002.12.03
申请号 JP19960238003 申请日期 1996.09.09
申请人 发明人
分类号 G06F7/38;G06F7/52;G06F7/535 主分类号 G06F7/38
代理机构 代理人
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