| 摘要 |
A memory controller portion of a DRAM is synchronized to a system clock, while an array portion of the DRAM is allowed to process signals at the array's natural frequency-independent of fixed timing parameters. By allowing the array portion to function at its natural frequency, the array's performance is not limited to "worst case" parameters; instead the DRAM can achieve maximize array performance at all voltage and temperature corners. The controller portion of the DRAM initiates an array access cycle, then waits until the array portion returns a data-valid signal. Since the array portion of the DRAM operates at its own natural frequency the data-valid signal can be completely asynchronous to the controller portion of the DRAM, which is operating in synchronization with a system clock. In order to ensure that the data-valid signal is latched properly, the controller sends an early version of the system clock to the data valid circuitry in the array portion of the DRAM. This early version of the system clock, known as the clock lockout signal, is used to effectively synchronize the output of the array portion to the controller portion, and thereby to the system clock.
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