| 摘要 |
PROBLEM TO BE SOLVED: To provide a static type semiconductor memory in which reduction of layout area is realized guaranteeing stability of holding data. SOLUTION: In this SRAM, refreshing of a system in which a word line potential VWL is reduced in pulse state between a reference potential VDD of a H level and a fixed potential Vc is performed. In this system, one period comprises an on (drive)-time t-on and an off(stop)-time t-off. A monitor node Mc and an inverter node Md in a monitor cell 250 imitated to a SRAM cell MC corresponds respectively to a data storage node Na and an inverter node Nb in the SRAM cell MC. A refreshing section 262 reduces the potential VWL of each word line WLBj to Vc with a fixed period Ts, at the same time, reduces a gate potential Vg of a PMOS transistor 252 in the monitor cell 250 with the prescribed depth (amplitude).
|
