发明名称 SIMULTANEOUS INTERRUPTION PROCESSOR, SIMULTANEOUS INTERRUPTION PROCESSING METHOD AND SIMULTANEOUS INTERRUPTION PROCESSING PROGRAM PERFORMED BY COMPUTER
摘要 PROBLEM TO BE SOLVED: To reduce overheads at the time of an interruption processing in a computer compared to a conventional case. SOLUTION: In the case that a prescribed number of events or messages are held, an interruption controller 3 holds the contents of the prescribed number of the events or the messages generated from magnetic disk controllers 4 and 5 or a LAN controller 6 and simultaneously reports them to an arithmetic unit 2. The arithmetic unit 2 preserves a software performance environment immediately before interruption generation, performs a processing corresponding to the contents of the prescribed number of the events or the messages and restores the software performance environment immediately before the interruption generation.
申请公布号 JP2002342093(A) 申请公布日期 2002.11.29
申请号 JP20010150738 申请日期 2001.05.21
申请人 KYUSHU UNIV 发明人 TANIGUCHI HIDEO;AMAMIYA MASATO
分类号 G06F13/24;G06F9/46;G06F9/48;(IPC1-7):G06F9/46 主分类号 G06F13/24
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