| 摘要 |
PROBLEM TO BE SOLVED: To provide a layouting method of a sense amplifier wherein a layout area of the sense amplifier is reduced to increase a process margin. SOLUTION: A plurality of bit lines and bit bar lines are alternately arranged parallel to each other. A single bit line and a single bit bar line constitute a paired single bit line. MOS transistors for a sense amplifier are alternately arranged in unit of two on a plurality of paired bit lines in its lengthwise direction. A gate of the MOS transistor for a sense amplifier is so formed as to almost cover the paired bit line. Thus, the layout area of the sense amplifier is reduced for increased process margin and wiring area, resulting in no gate wiring. |
