发明名称 HIGH-SPEED PLL CIRCUIT
摘要 PURPOSE: A high-speed PLL(Phase Locked Loop) circuit is provided to perform continuously an oscillating operation though an input voltage of 0 volt is applied. CONSTITUTION: A VCO(Voltage Controlled Oscillator) circuit(20') is formed with a VCO bias portion(22') and a VCO output portion(24'). The VCO bias portion(22') outputs bias voltages(VBIAS1',VBIAS2') to the VCO output portion(24') in response to a control signal(VCONTROL) when a control signal is in an active state. The VCO output portion(24') generates an output signal(fo) in response to the bias voltages(VBIAS1',VBIAS2'). The VCO bias portion(22') is formed with 4 PMOS transistors(MP10,MP12,MP14,MP16), 5 NMOS transistors(MN10,MN12,MN14,MN16,MN18), and a resistance. The VCO output portion(24') is formed with an operation amplifier, a VCO cell, and a ring oscillator.
申请公布号 KR20020088545(A) 申请公布日期 2002.11.29
申请号 KR20010027280 申请日期 2001.05.18
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 CHOI, CHANG HWI;KIM, SANG GON
分类号 H03L7/08;(IPC1-7):H03L7/08 主分类号 H03L7/08
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