| 摘要 |
PROBLEM TO BE SOLVED: To increase the number of pads for testing a wafer without increasing an area of a layout of a semiconductor integrated circuit device without forming the pad for testing the wafer on a scribing area. SOLUTION: A power line 13 and a ground line 15 are formed on an area between an internal cell area 7 of a semiconductor chip 3 and an I/O cell area 11. None is formed on the scribing area 5. A plurality of power source pads 17 for testing the wafer electrically connected to the line 13 are formed on the line 13. A plurality of ground pads 19 for testing the wafer electrically connected to the line 15 are formed on the line 15. In the case of testing the wafer, in addition to supplying a power to be executed via the pads 9 for the power source, the power is also supplied via the pads 17 for testing the wafer and the pads 19 for testing the wafer. |
